The present invention relates generally to memory devices, and more particularly, to an error-resilient memory device having row and/or column folding.
A conventional memory device includes multiple memory cells arranged in sets of rows and columns. The sets of rows and columns form a matrix of memory cells. The memory device further includes sets of word lines and bit lines. Word lines are connected to corresponding rows of the set of rows, and bit lines are connected to corresponding columns of the set of columns. Thus, the memory cells are connected to the bit lines corresponding to the columns of the memory cells and to the word lines corresponding to the rows of the memory cells. The memory cells store corresponding data bits received via the bit lines when corresponding ones of the word lines are active.
During fabrication of the memory device, variations in the manufacturing process can cause faults that damage one or more of the memory cells, which can corrupt data stored in the damaged cells. During testing of the memory device (performed after fabrication), damaged memory cells are identified and the memory device is discarded, resulting in loss of time and a waste of resources.
A known technique to avoid discarding memory devices with damaged memory cells is to alter the design of the memory device such that it is error-resilient. An error-resilient memory device includes sets of rows and columns of redundant memory cells in addition to the matrix of memory cells. The error-resilient memory device further includes corresponding sets of redundant word lines and bit lines. Hereinafter, the set of rows of redundant memory cells is referred to as “redundant rows”, and the set of columns of redundant memory cells is referred to as “redundant columns”.
The error-resilient memory device also includes a control circuit. When one or more of the memory cells are damaged, the rows and columns of memory cells corresponding to the damaged memory cells are referred to as damaged rows and damaged columns, respectively. During testing, the control circuit identifies the damaged memory cells and determines the number of redundant rows or redundant columns so that data is not stored in damaged cells. The control circuit also identifies at least one of the redundant rows and redundant columns based on the number of the redundant rows and redundant columns, and activates the corresponding redundant word lines and the redundant bit lines so that data will be stored in the redundant cells instead of the damaged cells. Thus, an error-resilient memory device with damaged cells does not necessarily need to be discarded after testing. However, the number of redundant memory cells is fixed and finite. Hence, if too many cells are damaged (when the number of faults in the error-resilient memory device is greater than a threshold number of faults), then the memory device must be discarded.
Often the variations in the manufacturing process generate a set of faults within a finite region of the memory device. Such faults are referred to as “concentrated faults”. Each damaged row and each damaged column include sets of damaged and undamaged memory cells. Although the undamaged memory cells within the finite region could store data, they are not used because they are not readily addressable and so the data is stored in the redundant rows/columns. This results in a waste of the undamaged cells. Thus, the memory repair efficiency of the error-resilient memory device is low.
It is known that the determination of the redundant rows and redundant columns is a non-deterministic polynomial time (NP) complete problem and hence, requires a complex control circuit. Such complex control circuitry increases the power consumption. Further, determination of the redundant rows and redundant columns is a time-consuming process. Thus, it would be advantageous to have a low power error-resilient memory device that makes efficient use of the memory cells and does not require complex control circuitry.